A systematic approach to building high performance software-based CRC generators

A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optimizing their memory requirement to meet the constraints of specific computer architectures. In addition, our algorithms can...

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Bibliographic Details
Main Authors: Kounavis, M.E., Berry, F.L.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Algorithm design and analysis
Buildings
Circuits
Computer architecture
Concurrent computing
Constraint optimization
Cyclic redundancy check
Research and development
Transport protocols
Online Access:Request full text
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Description
Summary:A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optimizing their memory requirement to meet the constraints of specific computer architectures. In addition, our algorithms can be implemented in software using commodity processors instead of specialized parallel circuits. We use this framework to design two efficient algorithms that run in the popular Intel IA32 processor architecture. First, a 'slicing-by-4' algorithm doubles the performance of existing software-based, table-driven CRC implementations based on the Sarwate (August 1988) algorithm while using a 4K cache footprint. Second, a 'slicing-by-8' algorithm triples the performance of existing software-based CRC implementations while using an 8K cache footprint.
ISSN:1530-1346
2642-7389
DOI:10.1109/ISCC.2005.18