An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology

An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 /spl mu/m/sup 2/ and 133 mm/sup 2/, respectively. Performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time fr...

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Bibliographic Details
Main Authors: Dae-Seok Byeon, Sung-Soo Lee, Young-Ho Lim, Jin-Sung Park, Wook-Kee Han, Pan-Suk Kwak, Dong-Hwan Kim, Dong-Hyuk Chae, Seung-Hyun Moon, Seung-Jae Lee, Hyun-Chul Cho, Jung-Woo Lee, Moo-Sung Kim, Joon-Sung Yang, Young-Woo Park, Duk-Won Bae, Jung-Dal Choi, Sung-Hoi Hur, Kang-Deog Suh
Format: Conference Proceeding
Language:English
Subjects:
Circuit noise
CMOS process
CMOS technology
Digital audio players
Digital cameras
Latches
Moon
Noise reduction
Threshold voltage
Universal Serial Bus
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Summary:An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 /spl mu/m/sup 2/ and 133 mm/sup 2/, respectively. Performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput to 23 MB/s.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1493861