A 126 mm/sup 2/ 4 Gb multilevel AG-AND flash memory with 10 MB/s programming throughput

A 4 Gb flash memory, fabricated in 90 nm CMOS technology, results in a 126 mm/sup 2/ chip size and a 0.0162 /spl mu/m/sup 2//b cell size. Address and temperature compensation methods control the resistance of the inversion-layer local bit-line. A programming throughput of 10 MB/s is achieved by usin...

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Bibliographic Details
Main Authors: Kurata, H., Sasago, Y., Otsuga, K., Arigane, T., Kawamura, T., Kobayashi, T., Kume, H., Homma, K., Kozakai, K., Noda, S., Ito, T., Shimizu, M., Ikeda, Y., Tsuchiya, O., Furusawa, K.
Format: Conference Proceeding
Language:English
Subjects:
CMOS process
Digital cameras
Flash memory
Indium tin oxide
Random access memory
Temperature control
Temperature dependence
Temperature distribution
Throughput
Voltage
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Summary:A 4 Gb flash memory, fabricated in 90 nm CMOS technology, results in a 126 mm/sup 2/ chip size and a 0.0162 /spl mu/m/sup 2//b cell size. Address and temperature compensation methods control the resistance of the inversion-layer local bit-line. A programming throughput of 10 MB/s is achieved by using a self-boosted charge injection scheme.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1493866