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A 22GS/s 6b DAC with integrated digital ramp generator
A 22GS/s 6b DAC is presented that includes a digital ramp pattern generator. The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3V/sub pp/ DNL
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container_end_page | 588 Vol. 1 |
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creator | Schvan, P. Pollex, D. Bellingrath, T. |
description | A 22GS/s 6b DAC is presented that includes a digital ramp pattern generator. The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3V/sub pp/ DNL |
doi_str_mv | 10.1109/ISSCC.2005.1493899 |
format | conference_proceeding |
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The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3V/sub pp/ DNL<0.5LSB and INL<0.9LSB are measured. The highest glitch energy is 0.5pVs. Settling times are 70 and 40ps for full- and half-scale transitions, respectively.</description><identifier>ISSN: 0193-6530</identifier><identifier>ISBN: 0780389042</identifier><identifier>ISBN: 9780780389045</identifier><identifier>EISSN: 2376-8606</identifier><identifier>DOI: 10.1109/ISSCC.2005.1493899</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; Clocks ; Counting circuits ; Digital-analog conversion ; Flip-flops ; Network synthesis ; Propagation delay ; Signal design ; Switches ; Synchronous generators</subject><ispartof>ISSCC. 2005 IEEE International Digest of Technical Papers. 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Solid-State Circuits Conference, 2005</title><addtitle>ISSCC</addtitle><description>A 22GS/s 6b DAC is presented that includes a digital ramp pattern generator. The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3V/sub pp/ DNL<0.5LSB and INL<0.9LSB are measured. The highest glitch energy is 0.5pVs. Settling times are 70 and 40ps for full- and half-scale transitions, respectively.</description><subject>Circuit simulation</subject><subject>Clocks</subject><subject>Counting circuits</subject><subject>Digital-analog conversion</subject><subject>Flip-flops</subject><subject>Network synthesis</subject><subject>Propagation delay</subject><subject>Signal design</subject><subject>Switches</subject><subject>Synchronous generators</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>0780389042</isbn><isbn>9780780389045</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj81Kw0AUhQd_wFr7ArqZF0h6587vXYZoa6HgIt2XaXITR9pakoD49gbs2Rz4Fh_nCPGsIFcKaLmpqrLMEcDmypAORDdihtq7LDhwt-IRfIAJg8E7MQNFOnNWw4NYDMMXTAnog4aZcIVEXFfLQbqDfC1K-ZPGT5nOI3d9HLmRTerSGI-yj6eL7PjME_7un8R9G48DL649F7vV2658z7Yf601ZbLNEMGbOe2MQQzDcoPFkjGZU1rqamahtfUPOYDhgmAYRxRAx1tZYdBqgVqjn4uVfm5h5f-nTKfa_--tj_QfOGURJ</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Schvan, P.</creator><creator>Pollex, D.</creator><creator>Bellingrath, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>A 22GS/s 6b DAC with integrated digital ramp generator</title><author>Schvan, P. ; Pollex, D. ; Bellingrath, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-6774422884ed2479443e21556cee99ff7d96428b2800899a8a2ac54526300c123</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Circuit simulation</topic><topic>Clocks</topic><topic>Counting circuits</topic><topic>Digital-analog conversion</topic><topic>Flip-flops</topic><topic>Network synthesis</topic><topic>Propagation delay</topic><topic>Signal design</topic><topic>Switches</topic><topic>Synchronous generators</topic><toplevel>online_resources</toplevel><creatorcontrib>Schvan, P.</creatorcontrib><creatorcontrib>Pollex, D.</creatorcontrib><creatorcontrib>Bellingrath, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEL</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Schvan, P.</au><au>Pollex, D.</au><au>Bellingrath, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 22GS/s 6b DAC with integrated digital ramp generator</atitle><btitle>ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005</btitle><stitle>ISSCC</stitle><date>2005</date><risdate>2005</risdate><spage>122</spage><epage>588 Vol. 1</epage><pages>122-588 Vol. 1</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>0780389042</isbn><isbn>9780780389045</isbn><abstract>A 22GS/s 6b DAC is presented that includes a digital ramp pattern generator. The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3V/sub pp/ DNL<0.5LSB and INL<0.9LSB are measured. The highest glitch energy is 0.5pVs. Settling times are 70 and 40ps for full- and half-scale transitions, respectively.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2005.1493899</doi></addata></record> |
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ispartof | ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.122-588 Vol. 1 |
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language | eng |
recordid | cdi_ieee_primary_1493899 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Circuit simulation Clocks Counting circuits Digital-analog conversion Flip-flops Network synthesis Propagation delay Signal design Switches Synchronous generators |
title | A 22GS/s 6b DAC with integrated digital ramp generator |
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