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A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply
A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing power consumption. The design operates at 3GHz with a 1.1V power supply.
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Main Authors: | , , , , , , , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Citations: | Items that cite this one |
Online Access: | Request full text |
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Summary: | A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing power consumption. The design operates at 3GHz with a 1.1V power supply. |
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ISSN: | 0193-6530 2376-8606 |
DOI: | 10.1109/ISSCC.2005.1494075 |