Loading…

A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing power consumption. The design operates at 3GHz with a 1.1V power supply.

Saved in:
Bibliographic Details
Main Authors: Zhang, K., Bhattacharya, U., Chen, Z., Hamzaoglu, F., Murray, D., Vallepalli, N., Wang, Y., Zheng, B., Bohr, M.
Format: Conference Proceeding
Language:English
Subjects:
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing power consumption. The design operates at 3GHz with a 1.1V power supply.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1494075