A novel CMOS compatible embedded nonvolatile memory with zero process adder

We demonstrate a CMOS compatible reprogrammable nonvolatile memory cell using a regular n-channel MOSFET with under-lapped source/drain diffusions that requires no extra processing steps in a standard 130nm CMOS logic technology. Experimental results indicate good endurance and retention characteris...

Full description

Saved in:
Bibliographic Details
Main Authors: Breitwisch, M.J., Lam, C.H., Johnson, J.B., Mittl, S.W.W., Zhu, J.W.
Format: Conference Proceeding
Language:English
Subjects:
CMOS logic circuits
CMOS process
CMOS technology
Conferences
Implants
Microelectronics
MOSFET circuits
Nonvolatile memory
Space technology
Threshold voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We demonstrate a CMOS compatible reprogrammable nonvolatile memory cell using a regular n-channel MOSFET with under-lapped source/drain diffusions that requires no extra processing steps in a standard 130nm CMOS logic technology. Experimental results indicate good endurance and retention characteristics. A strategy for optimizing programming efficiency is identified with the addition of one extra mask to introduce drain optimization implants.
ISSN:1087-4852
2576-9154
DOI:10.1109/MTDT.2005.12