New insight into stress induced voiding mechanism in Cu interconnects

An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary...

Full description

Saved in:
Bibliographic Details
Main Authors: Sun-Jung Lee, Soo-Geun Lee, Bong-Suk Suh, Hongjae Shin, Nae-In Lee, Ho-Kyu Kang, Gwangpyuk Suh
Format: Conference Proceeding
Language:English
Subjects:
Copper
Dielectrics
Failure analysis
Grain boundaries
High temperature superconductors
Inspection
Passivation
Stress
Testing
Wire
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 110
container_issue
container_start_page 108
container_title
container_volume
creator Sun-Jung Lee
Soo-Geun Lee
Bong-Suk Suh
Hongjae Shin
Nae-In Lee
Ho-Kyu Kang
Gwangpyuk Suh
description An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.
doi_str_mv 10.1109/IITC.2005.1499943
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1499943</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1499943</ieee_id><sourcerecordid>1499943</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-b23d7052b03c808be8ec33088521cd0857cc6dd8996398fe9ee3275aab1cd4193</originalsourceid><addsrcrecordid>eNo9kE9Lw0AUxBf_gLX2A4iXfIHEt_uy2bdHCbUWil4q9FaS3dd2xSSSTRW_vRGLc5mB3zCHEeJWQiYl2Pvlcl1mCkBnMrfW5ngmJgoJ0gKRzsU1GAIko9Xm4h-ozZWYxfgGo9BqzHEi5s_8lYQ2hv1hGH3okjj0HOOY_dGxTz674EO7Txp2h6oNsRlJUh5_u9y7rm3ZDfFGXO6q98izk0_F6-N8XT6lq5fFsnxYpUEaPaS1Qm9AqxrQEVDNxA4RiLSSzgNp41zhPVlboKUdW2ZURldVPeJcWpyKu7_dwMzbjz40Vf-9PT2APwBTTaY</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>New insight into stress induced voiding mechanism in Cu interconnects</title><source>IEEE Xplore All Conference Series</source><creator>Sun-Jung Lee ; Soo-Geun Lee ; Bong-Suk Suh ; Hongjae Shin ; Nae-In Lee ; Ho-Kyu Kang ; Gwangpyuk Suh</creator><creatorcontrib>Sun-Jung Lee ; Soo-Geun Lee ; Bong-Suk Suh ; Hongjae Shin ; Nae-In Lee ; Ho-Kyu Kang ; Gwangpyuk Suh</creatorcontrib><description>An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.</description><identifier>ISSN: 2380-632X</identifier><identifier>ISBN: 078038752X</identifier><identifier>ISBN: 9780780387522</identifier><identifier>EISSN: 2380-6338</identifier><identifier>DOI: 10.1109/IITC.2005.1499943</identifier><language>eng</language><publisher>IEEE</publisher><subject>Copper ; Dielectrics ; Failure analysis ; Grain boundaries ; High temperature superconductors ; Inspection ; Passivation ; Stress ; Testing ; Wire</subject><ispartof>Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005, 2005, p.108-110</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1499943$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1499943$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sun-Jung Lee</creatorcontrib><creatorcontrib>Soo-Geun Lee</creatorcontrib><creatorcontrib>Bong-Suk Suh</creatorcontrib><creatorcontrib>Hongjae Shin</creatorcontrib><creatorcontrib>Nae-In Lee</creatorcontrib><creatorcontrib>Ho-Kyu Kang</creatorcontrib><creatorcontrib>Gwangpyuk Suh</creatorcontrib><title>New insight into stress induced voiding mechanism in Cu interconnects</title><title>Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005</title><addtitle>IITC</addtitle><description>An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.</description><subject>Copper</subject><subject>Dielectrics</subject><subject>Failure analysis</subject><subject>Grain boundaries</subject><subject>High temperature superconductors</subject><subject>Inspection</subject><subject>Passivation</subject><subject>Stress</subject><subject>Testing</subject><subject>Wire</subject><issn>2380-632X</issn><issn>2380-6338</issn><isbn>078038752X</isbn><isbn>9780780387522</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9kE9Lw0AUxBf_gLX2A4iXfIHEt_uy2bdHCbUWil4q9FaS3dd2xSSSTRW_vRGLc5mB3zCHEeJWQiYl2Pvlcl1mCkBnMrfW5ngmJgoJ0gKRzsU1GAIko9Xm4h-ozZWYxfgGo9BqzHEi5s_8lYQ2hv1hGH3okjj0HOOY_dGxTz674EO7Txp2h6oNsRlJUh5_u9y7rm3ZDfFGXO6q98izk0_F6-N8XT6lq5fFsnxYpUEaPaS1Qm9AqxrQEVDNxA4RiLSSzgNp41zhPVlboKUdW2ZURldVPeJcWpyKu7_dwMzbjz40Vf-9PT2APwBTTaY</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Sun-Jung Lee</creator><creator>Soo-Geun Lee</creator><creator>Bong-Suk Suh</creator><creator>Hongjae Shin</creator><creator>Nae-In Lee</creator><creator>Ho-Kyu Kang</creator><creator>Gwangpyuk Suh</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>New insight into stress induced voiding mechanism in Cu interconnects</title><author>Sun-Jung Lee ; Soo-Geun Lee ; Bong-Suk Suh ; Hongjae Shin ; Nae-In Lee ; Ho-Kyu Kang ; Gwangpyuk Suh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-b23d7052b03c808be8ec33088521cd0857cc6dd8996398fe9ee3275aab1cd4193</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Copper</topic><topic>Dielectrics</topic><topic>Failure analysis</topic><topic>Grain boundaries</topic><topic>High temperature superconductors</topic><topic>Inspection</topic><topic>Passivation</topic><topic>Stress</topic><topic>Testing</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Sun-Jung Lee</creatorcontrib><creatorcontrib>Soo-Geun Lee</creatorcontrib><creatorcontrib>Bong-Suk Suh</creatorcontrib><creatorcontrib>Hongjae Shin</creatorcontrib><creatorcontrib>Nae-In Lee</creatorcontrib><creatorcontrib>Ho-Kyu Kang</creatorcontrib><creatorcontrib>Gwangpyuk Suh</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sun-Jung Lee</au><au>Soo-Geun Lee</au><au>Bong-Suk Suh</au><au>Hongjae Shin</au><au>Nae-In Lee</au><au>Ho-Kyu Kang</au><au>Gwangpyuk Suh</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>New insight into stress induced voiding mechanism in Cu interconnects</atitle><btitle>Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005</btitle><stitle>IITC</stitle><date>2005</date><risdate>2005</risdate><spage>108</spage><epage>110</epage><pages>108-110</pages><issn>2380-632X</issn><eissn>2380-6338</eissn><isbn>078038752X</isbn><isbn>9780780387522</isbn><abstract>An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.</abstract><pub>IEEE</pub><doi>10.1109/IITC.2005.1499943</doi><tpages>3</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 2380-632X
ispartof Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005, 2005, p.108-110
issn 2380-632X
2380-6338
language eng
recordid cdi_ieee_primary_1499943
source IEEE Xplore All Conference Series
subjects Copper
Dielectrics
Failure analysis
Grain boundaries
High temperature superconductors
Inspection
Passivation
Stress
Testing
Wire
title New insight into stress induced voiding mechanism in Cu interconnects
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T17%3A20%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=New%20insight%20into%20stress%20induced%20voiding%20mechanism%20in%20Cu%20interconnects&rft.btitle=Proceedings%20of%20the%20IEEE%202005%20International%20Interconnect%20Technology%20Conference,%202005&rft.au=Sun-Jung%20Lee&rft.date=2005&rft.spage=108&rft.epage=110&rft.pages=108-110&rft.issn=2380-632X&rft.eissn=2380-6338&rft.isbn=078038752X&rft.isbn_list=9780780387522&rft_id=info:doi/10.1109/IITC.2005.1499943&rft_dat=%3Cieee_CHZPO%3E1499943%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-b23d7052b03c808be8ec33088521cd0857cc6dd8996398fe9ee3275aab1cd4193%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1499943&rfr_iscdi=true