Challenges in implementing high-k dielectrics in the 45nm technology node

Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced ga...

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Bibliographic Details
Main Authors: Lee, B.H., Song, S.C., Choi, R., Wen, H.C., Majhi, P., Kirsch, P., Young, C., Bersuker, G.
Format: Conference Proceeding
Language:English
Subjects:
CMOS technology
Degradation
Electrodes
High K dielectric materials
High-K gate dielectrics
Inorganic materials
Leakage current
MOSFETs
Optical scattering
Phonons
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Summary:Metal/high-k gate stack technology is urgently required to continue the scaling of CMOS devices at the 45nm node. However, the challenges of simultaneously implementing metal gate and high-k gate dielectrics into the 45nm technology node have not been addressed. This paper reviews recent advanced gate stack technology to illuminate some of the technical challenges in this area.
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2005.1502595