An Integrated Test Platform for Nanostructure Electrical Characterization

We have designed and fabricated a fully-integrated CMOS-based lab-on-a-chip electronics platform to investigate the electrical characteristics of novel nanoelectronic devices. In contrast with previous work which requires the use of external equipment, therefore limiting the range of possible measur...

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Bibliographic Details
Main Authors: Duval, O., Lafrance, L.-P., Savaria, Y., Desjardins, P.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance measurement
CMOS integrated circuits
Current measurement
Electric variables
Inductance measurement
Integrated circuit measurements
Lab-on-a-chip
Nanoscale devices
Parasitic capacitance
Testing
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Summary:We have designed and fabricated a fully-integrated CMOS-based lab-on-a-chip electronics platform to investigate the electrical characteristics of novel nanoelectronic devices. In contrast with previous work which requires the use of external equipment, therefore limiting the range of possible measurements due to parasitic capacitance and inductance, we embed the nanostructures on an integrated circuit produced with a mature 180-nm CMOS process. The test platform includes modules for measuring I-V curves with a driven current range from 100 pA to 100 µA, and a measured voltage in the 0-1.5 V range. Propagation delay measurement modules as fine as 7 ps are also included. Inputs-outputs and test configurations are controlled using a standard IEEE 1149.1 JTAG scan chain.
DOI:10.1109/ICMENS.2004.1508953