Analytical delay computation for arbitrary distributed RLC trees

As feature size decreases and circuit size and complexity increases, interconnect plays a dominating role in determining the overall circuit performance, reliability and cost. With decreasing feature sizes, the delay due to the resistance and capacitance of on-chip interconnects increasingly dominat...

Full description

Saved in:
Bibliographic Details
Main Authors: Coulibaly, L.M., Kadim, H.J.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Circuit optimization
Delay effects
Delay estimation
Distributed computing
Equations
Frequency
Integrated circuit interconnections
Transfer functions
Very large scale integration
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:As feature size decreases and circuit size and complexity increases, interconnect plays a dominating role in determining the overall circuit performance, reliability and cost. With decreasing feature sizes, the delay due to the resistance and capacitance of on-chip interconnects increasingly dominates the delay due to transistors. In this paper, we present a closed-form delay calculation approach for distributed RLC interconnect trees that addresses shortcomings with past interconnect models.
DOI:10.1109/ISSCS.2005.1511341