A low-overhead virtual rail technique for SRAM leakage power reduction

We propose a virtual supply rail control technique that reduces SRAM leakage. This method encompasses a cell-based image, serial tiling, pitch matching, small drive device overhead, and controlled power-on currents while incurring small circuit overhead. A virtual rail cell contains both the sleep t...

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Bibliographic Details
Main Authors: Kuang, J.B., Ngo, H.C., Nowka, K.J., Law, J.C., Joshi, R.V.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Delay
Inverters
Laboratories
Load flow
Performance analysis
Rails
Random access memory
Switches
Voltage
Online Access:Request full text
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Summary:We propose a virtual supply rail control technique that reduces SRAM leakage. This method encompasses a cell-based image, serial tiling, pitch matching, small drive device overhead, and controlled power-on currents while incurring small circuit overhead. A virtual rail cell contains both the sleep transistor fingers and input/output drive transistors. The usual overhead associated with the drive circuit that controls the sleep transistors is significantly reduced due to reduced wire load and improved drive efficiency. This technique provides gradual power-on characteristics and good signal slews while effectively mitigating leakage current, maintaining read/write speed and achieving power-on latency compatible with high-performance designs.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2005.11