A high speed scalable shift-register based on-chip serial communication design for SoC applications

In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmi...

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Bibliographic Details
Main Authors: I-Chyn Wey, You-Gang Chen, Chia-Tsun Wu, Wei Wang, An-Yeu Wu
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Circuits
Clocks
Communication system control
Design engineering
Ring oscillators
Shift registers
System-on-a-chip
Transmitters
Wire
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Summary:In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design (Kimura et al., 2003).
DOI:10.1109/RME.2005.1543012