A new dynamic gate capacitance measurement protocol to evaluate integrated high-voltage devices' switching loss performances in power management applications

A novel dynamic gate capacitance characterization technique is proposed to evaluate switching losses in power devices. Dynamic gate capacitance is obtained by measuring the gate displacement current due to the application of a controlled gate voltage pulse, closely matching real operation conditions...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2005-12, Vol.52 (12), p.2769-2775
Main Authors: Grelu, C., Baboux, N., Bianchi, R.A., Plossu, C.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
Capacitance measurement
CMOS
CMOS integrated circuits
Design. Technologies. Operation analysis. Testing
Devices
Dynamic tests
Dynamics
Electronics
Exact sciences and technology
FET switches
Gates
Integrated circuits
Losses
Management
Miller effect
MOSFETs
Power FETs
Power integrated circuits
power losses
Power management
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Switching
switching characterization
Transistors
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Description
Summary:A novel dynamic gate capacitance characterization technique is proposed to evaluate switching losses in power devices. Dynamic gate capacitance is obtained by measuring the gate displacement current due to the application of a controlled gate voltage pulse, closely matching real operation conditions of power switches. Several architectures for 20-V MOSFET transistors, integrated in a low-cost power management 0.13-/spl mu/m CMOS technology, are studied. Experimental results are compared to a specific small-signal model for switching transition gate capacitance.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2005.859659