Effect of tensile capping layer on 3-D stress profiles in FinFET channels

Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-...

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Bibliographic Details
Main Authors: Kyoungsub Shin, Lauderdale, T., Tsu-Jae King
Format: Conference Proceeding
Language:English
Subjects:
Capacitive sensors
Compressive stress
Crystallization
Electronic mail
FETs
FinFETs
Mechanical engineering
MOSFETs
Silicon on insulator technology
Tensile stress
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Summary:Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator
ISSN:1548-3770
2640-6853
DOI:10.1109/DRC.2005.1553120