LDPC Code for Reduced Routing Decoder

A design approach that reduces the routing complexity in a VLSI implementation of low-density parity-check (LDPC) decoder is presented. An LDPC code is a linear-block code for forward error correction, attributed by a sparse parity-check matrix. Iterative decoding of this code is shown to yield bit...

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Bibliographic Details
Main Authors: Euncheol Kim, Choi, G.S.
Format: Conference Proceeding
Language:English
Subjects:
Bit error rate
Forward error correction
Iterative decoding
Logic
Parity check codes
Routing
Sparse matrices
Throughput
Very large scale integration
Wires
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Summary:A design approach that reduces the routing complexity in a VLSI implementation of low-density parity-check (LDPC) decoder is presented. An LDPC code is a linear-block code for forward error correction, attributed by a sparse parity-check matrix. Iterative decoding of this code is shown to yield bit error rate (BER) performance approaching Shannon limit. However, implementation of decoder for this code is difficult due to the routing requirements of its massive number of data-flow structures in decoding logic. We present a routing approach for a parallel LDPC decoder implementation by 1) analyzing the physical routability limitations and 2) designing the code parameters to limit the interconnect lengths to a bounded region. The approach does not compromise the BER performance, and yet achieves a much higher throughput resulting from significantly reduced wires lengths
ISSN:2163-0771
DOI:10.1109/APCC.2005.1554212