FinFET Source/Drain Profile Optimization Considering GIDL for Low Power Applications

We have investigated sub-50nm FinFET design to be used in low power applications, through 3D device simulations considering gate-induced drain leakage (GEDL). It is found that the body-tied structure is necessary for dopedchannel FinFET to reduce off-state current (I off ). For further reduction of...

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Bibliographic Details
Main Authors: Tanaka, K., Takeuchi, K., Hane, M.
Format: Conference Proceeding
Language:English
Subjects:
CMOS process
Current measurement
Design methodology
Doping profiles
FinFETs
Manufacturing processes
MOSFET circuits
National electric code
Silicon on insulator technology
Tunneling
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Summary:We have investigated sub-50nm FinFET design to be used in low power applications, through 3D device simulations considering gate-induced drain leakage (GEDL). It is found that the body-tied structure is necessary for dopedchannel FinFET to reduce off-state current (I off ). For further reduction of I off including GIDL, optimization of source/drain (S/D) profile characterized by lateral spread σ and lateral offset δ is effective, and feasibility of S/D profile depends on channel doping concentration. By adjusting the concentration properly, loff can be reduced for (σ,δ) points in a wide range. In addition, sensitivity of drive current upon σ and δ is found to be small.
ISSN:1946-1569
1946-1577
DOI:10.1109/SISPAD.2005.201528