A frequency synthesizer architecture using frequency difference detection

In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off...

Full description

Saved in:
Bibliographic Details
Main Authors: Albrecht, S., Sumi, Y., Ismail, M., Tenhunen, H.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Counting circuits
Delay effects
Digital signal processing
Feedback
Frequency conversion
Frequency synthesizers
Signal processing
Voltage control
Voltage-controlled oscillators
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2003.1562498