A frequency synthesizer architecture using frequency difference detection

In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off...

Full description

Saved in:
Bibliographic Details
Main Authors: Albrecht, S., Sumi, Y., Ismail, M., Tenhunen, H.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Counting circuits
Delay effects
Digital signal processing
Feedback
Frequency conversion
Frequency synthesizers
Signal processing
Voltage control
Voltage-controlled oscillators
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 1157 Vol. 3
container_issue
container_start_page 1155
container_title
container_volume 3
creator Albrecht, S.
Sumi, Y.
Ismail, M.
Tenhunen, H.
description In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.
doi_str_mv 10.1109/MWSCAS.2003.1562498
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1562498</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1562498</ieee_id><sourcerecordid>1562498</sourcerecordid><originalsourceid>FETCH-LOGICAL-i213t-adaf9a4346d5cb478a446f479f83b25620e8df06a9e47a5baa00cd3132684e193</originalsourceid><addsrcrecordid>eNpNkMtOwzAURC0eEm3hC7rJD6TYvjeOvYwiHpWKWBTEsnLia2oEAexkEb6eVHTBakaao5FmGFsKvhKCm-uHl21dbVeSc1iJQkk0-oTNRFHoHLQxp2zOS81BS4NwdghwCkpUF2ye0hvnEkphZmxdZT7S90BdO2Zp7Po9pfBDMbOx3Yee2n6IlA0pdK__QBe8pzhZyhwdoPDZXbJzb98TXR11wZ5vb57q-3zzeLeuq00epIA-t856YxFQuaJtsNQWUXksjdfQyGkIJ-08V9YQlrZorOW8dSBAKo0kDCzY8q83ENHuK4YPG8fd8QL4BQNZT-8</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A frequency synthesizer architecture using frequency difference detection</title><source>IEEE Xplore All Conference Series</source><creator>Albrecht, S. ; Sumi, Y. ; Ismail, M. ; Tenhunen, H.</creator><creatorcontrib>Albrecht, S. ; Sumi, Y. ; Ismail, M. ; Tenhunen, H.</creatorcontrib><description>In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.</description><identifier>ISSN: 1548-3746</identifier><identifier>ISBN: 0780382943</identifier><identifier>ISBN: 9780780382947</identifier><identifier>EISSN: 1558-3899</identifier><identifier>DOI: 10.1109/MWSCAS.2003.1562498</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Counting circuits ; Delay effects ; Digital signal processing ; Feedback ; Frequency conversion ; Frequency synthesizers ; Signal processing ; Voltage control ; Voltage-controlled oscillators</subject><ispartof>2003 46th Midwest Symposium on Circuits and Systems, 2003, Vol.3, p.1155-1157 Vol. 3</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1562498$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,4050,4051,23930,23931,25140,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1562498$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Albrecht, S.</creatorcontrib><creatorcontrib>Sumi, Y.</creatorcontrib><creatorcontrib>Ismail, M.</creatorcontrib><creatorcontrib>Tenhunen, H.</creatorcontrib><title>A frequency synthesizer architecture using frequency difference detection</title><title>2003 46th Midwest Symposium on Circuits and Systems</title><addtitle>MWSCAS</addtitle><description>In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.</description><subject>Clocks</subject><subject>Counting circuits</subject><subject>Delay effects</subject><subject>Digital signal processing</subject><subject>Feedback</subject><subject>Frequency conversion</subject><subject>Frequency synthesizers</subject><subject>Signal processing</subject><subject>Voltage control</subject><subject>Voltage-controlled oscillators</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>0780382943</isbn><isbn>9780780382947</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpNkMtOwzAURC0eEm3hC7rJD6TYvjeOvYwiHpWKWBTEsnLia2oEAexkEb6eVHTBakaao5FmGFsKvhKCm-uHl21dbVeSc1iJQkk0-oTNRFHoHLQxp2zOS81BS4NwdghwCkpUF2ye0hvnEkphZmxdZT7S90BdO2Zp7Po9pfBDMbOx3Yee2n6IlA0pdK__QBe8pzhZyhwdoPDZXbJzb98TXR11wZ5vb57q-3zzeLeuq00epIA-t856YxFQuaJtsNQWUXksjdfQyGkIJ-08V9YQlrZorOW8dSBAKo0kDCzY8q83ENHuK4YPG8fd8QL4BQNZT-8</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Albrecht, S.</creator><creator>Sumi, Y.</creator><creator>Ismail, M.</creator><creator>Tenhunen, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2003</creationdate><title>A frequency synthesizer architecture using frequency difference detection</title><author>Albrecht, S. ; Sumi, Y. ; Ismail, M. ; Tenhunen, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i213t-adaf9a4346d5cb478a446f479f83b25620e8df06a9e47a5baa00cd3132684e193</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Clocks</topic><topic>Counting circuits</topic><topic>Delay effects</topic><topic>Digital signal processing</topic><topic>Feedback</topic><topic>Frequency conversion</topic><topic>Frequency synthesizers</topic><topic>Signal processing</topic><topic>Voltage control</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Albrecht, S.</creatorcontrib><creatorcontrib>Sumi, Y.</creatorcontrib><creatorcontrib>Ismail, M.</creatorcontrib><creatorcontrib>Tenhunen, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Explore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Albrecht, S.</au><au>Sumi, Y.</au><au>Ismail, M.</au><au>Tenhunen, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A frequency synthesizer architecture using frequency difference detection</atitle><btitle>2003 46th Midwest Symposium on Circuits and Systems</btitle><stitle>MWSCAS</stitle><date>2003</date><risdate>2003</risdate><volume>3</volume><spage>1155</spage><epage>1157 Vol. 3</epage><pages>1155-1157 Vol. 3</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>0780382943</isbn><isbn>9780780382947</isbn><abstract>In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2003.1562498</doi></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1548-3746
ispartof 2003 46th Midwest Symposium on Circuits and Systems, 2003, Vol.3, p.1155-1157 Vol. 3
issn 1548-3746
1558-3899
language eng
recordid cdi_ieee_primary_1562498
source IEEE Xplore All Conference Series
subjects Clocks
Counting circuits
Delay effects
Digital signal processing
Feedback
Frequency conversion
Frequency synthesizers
Signal processing
Voltage control
Voltage-controlled oscillators
title A frequency synthesizer architecture using frequency difference detection
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T15%3A09%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20frequency%20synthesizer%20architecture%20using%20frequency%20difference%20detection&rft.btitle=2003%2046th%20Midwest%20Symposium%20on%20Circuits%20and%20Systems&rft.au=Albrecht,%20S.&rft.date=2003&rft.volume=3&rft.spage=1155&rft.epage=1157%20Vol.%203&rft.pages=1155-1157%20Vol.%203&rft.issn=1548-3746&rft.eissn=1558-3899&rft.isbn=0780382943&rft.isbn_list=9780780382947&rft_id=info:doi/10.1109/MWSCAS.2003.1562498&rft_dat=%3Cieee_CHZPO%3E1562498%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i213t-adaf9a4346d5cb478a446f479f83b25620e8df06a9e47a5baa00cd3132684e193%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1562498&rfr_iscdi=true