Dynamic circuit techniques using independently controlled double-gate devices

In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the d...

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Bibliographic Details
Main Authors: Kuang, J.B., Kim, K., Chuang, C.T., Ngo, H.C., Nowka, K.J.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Circuit noise
Circuit synthesis
Degradation
Delay effects
Employment
Laboratories
Logic devices
Logic gates
Robustness
Online Access:Request full text
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Description
Summary:In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2005.1563539