Enhanced write performance of a 64-mb phase-change random access memory

The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-/spl mu/m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed,...

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Published in:IEEE journal of solid-state circuits 2006-01, Vol.41 (1), p.122-126
Main Authors: OH, Hyung-Rok, CHO, Beak-Hyung, JEONG, Gi-Tae, JEONG, Hong-Sik, KIM, Kinam, WOO YEONG CHO, KANG, Sangbeom, CHOI, Byung-Gil, KIM, Hye-Jin, KIM, Ki-Sung, KIM, Du-Eung, KWAK, Choong-Keun, BYUN, Hyun-Geun
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Language:English
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Summary:The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-/spl mu/m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2005.859016