Scalable bus interface for HSDPA co-processor extension

This paper presents a scalable bus developed for HSDPA co-processor extension of W-CDMA digital baseband processors. The use of two separate buses (one for control messages and one for transmission and reception data) in a multimaster bus design helps keep down bus occupancy and CPU loads. The desig...

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Bibliographic Details
Main Authors: Takeuchi, T., Igura, H., Hashimoto, T., Tsumura, S., Nishi, N.
Format: Conference Proceeding
Language:English
Subjects:
Automatic repeat request
Baseband
Coprocessors
Downlink
Large scale integration
Multiaccess communication
Multimedia communication
National electric code
Radio broadcasting
Scalability
Online Access:Request full text
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Summary:This paper presents a scalable bus developed for HSDPA co-processor extension of W-CDMA digital baseband processors. The use of two separate buses (one for control messages and one for transmission and reception data) in a multimaster bus design helps keep down bus occupancy and CPU loads. The design offers high scalability for future extension and single-chip implementation, as well as a 66% reduction in bus occupancy over that of conventional memory bus connections. Further, with the addition of a MAC accelerator, the design achieves a 45% CPU-load reduction.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2005.1568605