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Efficient compression of deterministic patterns into multiple PRPG seeds
Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application t...
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creator | Wohl, P. Waicukauski, J.A. Patel, S. DaSilva, F. Williams, T.W. Kapur, R. |
description | Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression |
doi_str_mv | 10.1109/TEST.2005.1584057 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1584057</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1584057</ieee_id><sourcerecordid>1584057</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-a7799a74d6aed435fbcd67b2472b13ef2314c9a7903fd99a0a5f20ebe30bbbfd3</originalsourceid><addsrcrecordid>eNotkMtqwzAUREUfUDfNB5Ru9AN2ryTLspYluEkg0NB6HyTrClT8wlIX_fsaGhgYBg7DMIQ8MygYA_3aNl9twQFkwWRdglQ3JONC1TnnEm7JVqsaVgkNoq7uSMag1rmQQj-Qxxi_AThIDhk5NN6HLuCYaDcN84Ixhmmkk6cOEy5DGENMoaOzSWscIw1jmujw06cw90jPn-c9jYguPpF7b_qI26tvSPvetLtDfvrYH3dvpzxoSLlRSmujSlcZdKWQ3nauUpaXilsm0HPBym4F1tnerSQY6TmgRQHWWu_Ehrz81wZEvMxLGMzye7l-IP4AEvxPiQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Efficient compression of deterministic patterns into multiple PRPG seeds</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Wohl, P. ; Waicukauski, J.A. ; Patel, S. ; DaSilva, F. ; Williams, T.W. ; Kapur, R.</creator><creatorcontrib>Wohl, P. ; Waicukauski, J.A. ; Patel, S. ; DaSilva, F. ; Williams, T.W. ; Kapur, R.</creatorcontrib><description>Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression</description><identifier>ISSN: 1089-3539</identifier><identifier>ISBN: 9780780390386</identifier><identifier>ISBN: 0780390385</identifier><identifier>EISSN: 2378-2250</identifier><identifier>DOI: 10.1109/TEST.2005.1584057</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automatic test pattern generation ; Built-in self-test ; Circuit faults ; Circuit testing ; Clocks ; Codecs ; Costs ; Delay ; Merging ; Wiring</subject><ispartof>IEEE International Conference on Test, 2005, 2005, p.10 pp.-925</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1584057$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,4036,4037,27906,54536,54901,54913</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1584057$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Wohl, P.</creatorcontrib><creatorcontrib>Waicukauski, J.A.</creatorcontrib><creatorcontrib>Patel, S.</creatorcontrib><creatorcontrib>DaSilva, F.</creatorcontrib><creatorcontrib>Williams, T.W.</creatorcontrib><creatorcontrib>Kapur, R.</creatorcontrib><title>Efficient compression of deterministic patterns into multiple PRPG seeds</title><title>IEEE International Conference on Test, 2005</title><addtitle>TEST</addtitle><description>Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression</description><subject>Automatic test pattern generation</subject><subject>Built-in self-test</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Clocks</subject><subject>Codecs</subject><subject>Costs</subject><subject>Delay</subject><subject>Merging</subject><subject>Wiring</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>9780780390386</isbn><isbn>0780390385</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkMtqwzAUREUfUDfNB5Ru9AN2ryTLspYluEkg0NB6HyTrClT8wlIX_fsaGhgYBg7DMIQ8MygYA_3aNl9twQFkwWRdglQ3JONC1TnnEm7JVqsaVgkNoq7uSMag1rmQQj-Qxxi_AThIDhk5NN6HLuCYaDcN84Ixhmmkk6cOEy5DGENMoaOzSWscIw1jmujw06cw90jPn-c9jYguPpF7b_qI26tvSPvetLtDfvrYH3dvpzxoSLlRSmujSlcZdKWQ3nauUpaXilsm0HPBym4F1tnerSQY6TmgRQHWWu_Ehrz81wZEvMxLGMzye7l-IP4AEvxPiQ</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Wohl, P.</creator><creator>Waicukauski, J.A.</creator><creator>Patel, S.</creator><creator>DaSilva, F.</creator><creator>Williams, T.W.</creator><creator>Kapur, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>Efficient compression of deterministic patterns into multiple PRPG seeds</title><author>Wohl, P. ; Waicukauski, J.A. ; Patel, S. ; DaSilva, F. ; Williams, T.W. ; Kapur, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-a7799a74d6aed435fbcd67b2472b13ef2314c9a7903fd99a0a5f20ebe30bbbfd3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Automatic test pattern generation</topic><topic>Built-in self-test</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Clocks</topic><topic>Codecs</topic><topic>Costs</topic><topic>Delay</topic><topic>Merging</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Wohl, P.</creatorcontrib><creatorcontrib>Waicukauski, J.A.</creatorcontrib><creatorcontrib>Patel, S.</creatorcontrib><creatorcontrib>DaSilva, F.</creatorcontrib><creatorcontrib>Williams, T.W.</creatorcontrib><creatorcontrib>Kapur, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wohl, P.</au><au>Waicukauski, J.A.</au><au>Patel, S.</au><au>DaSilva, F.</au><au>Williams, T.W.</au><au>Kapur, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Efficient compression of deterministic patterns into multiple PRPG seeds</atitle><btitle>IEEE International Conference on Test, 2005</btitle><stitle>TEST</stitle><date>2005</date><risdate>2005</risdate><spage>10 pp.</spage><epage>925</epage><pages>10 pp.-925</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>9780780390386</isbn><isbn>0780390385</isbn><abstract>Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression</abstract><pub>IEEE</pub><doi>10.1109/TEST.2005.1584057</doi></addata></record> |
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subjects | Automatic test pattern generation Built-in self-test Circuit faults Circuit testing Clocks Codecs Costs Delay Merging Wiring |
title | Efficient compression of deterministic patterns into multiple PRPG seeds |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T06%3A34%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Efficient%20compression%20of%20deterministic%20patterns%20into%20multiple%20PRPG%20seeds&rft.btitle=IEEE%20International%20Conference%20on%20Test,%202005&rft.au=Wohl,%20P.&rft.date=2005&rft.spage=10%20pp.&rft.epage=925&rft.pages=10%20pp.-925&rft.issn=1089-3539&rft.eissn=2378-2250&rft.isbn=9780780390386&rft.isbn_list=0780390385&rft_id=info:doi/10.1109/TEST.2005.1584057&rft_dat=%3Cieee_6IE%3E1584057%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-a7799a74d6aed435fbcd67b2472b13ef2314c9a7903fd99a0a5f20ebe30bbbfd3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1584057&rfr_iscdi=true |