Node sensitivity analysis for soft errors in CMOS logic

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using cha...

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Bibliographic Details
Main Authors: Gill, B.S., Papachristou, C., Wolff, F.G., Seifert, N.
Format: Conference Proceeding
Language:English
Subjects:
Automatic logic units
Automatic test pattern generation
Circuit simulation
CMOS logic circuits
Computational modeling
Libraries
Logic testing
Sensitivity analysis
Single event upset
Timing
Online Access:Request full text
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Description
Summary:In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100 nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2005.1584062