Memory-fast interfaces for DRAMs

The limitations of current nominal 5 V interfaces are examined, and the requirements for interfaces between high-speed DRAMs and processors are outlined. Three solutions are described. One is a center-tap-terminated interface, the second uses Gunning transceiver logic, and the third relies on low-vo...

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Bibliographic Details
Published in:IEEE spectrum 1992-10, Vol.29 (10), p.54-57
Main Authors: Foss, R.C., Prince, B., Rodgers, R., Gustavson, D.B., James, D.V., Stone, G., Kempainen, S.
Format: Magazinearticle
Language:English
Subjects:
BiCMOS integrated circuits
Bipolar transistors
Circuit testing
CMOS technology
Costs
Logic circuits
Logic devices
Pins
Rail to rail outputs
Random access memory
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Description
Summary:The limitations of current nominal 5 V interfaces are examined, and the requirements for interfaces between high-speed DRAMs and processors are outlined. Three solutions are described. One is a center-tap-terminated interface, the second uses Gunning transceiver logic, and the third relies on low-voltage differential signaling.< >
ISSN:0018-9235
1939-9340
DOI:10.1109/6.158639