Fast identification of robust dependent path delay faults

• Main Authors: Sparmann, U., Luxenburger, D., Cheng, K.-T., Reddy, S. M.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuit faults; Circuit testing; Computer aided manufacturing; Computer science; Delay; Digital circuits; Fault diagnosis; Hardware > Hardware test > Test-pattern generation and fault simulation; Hardware > Integrated circuits > Logic circuits; Logic testing; Robustness; Timing
• ISSN: 0738-100X
• DOI: 10.1145/217474.217517

Recently, it has been shown in [1] and [2] that in order to verify the correct timing of a manufactured circuit not all of its paths need to be considered for delay testing. In this paper, a theory is developed which puts the work of these papers into a common framework, thus allowing for a better understanding of their relation. In addition, we consider the computational problem of identifying large sets of such not-necessary-to-test paths. Since the approach of [1] can only be applied for small scale circuits, we develop a new algorithm which trades quality of the result against computation time, and allows handling of large circuits with tens of millions of paths. Experimental results show that enormous improvements in running time are only paid for by a small decrease in quality.