A 2.5-Gb/s clock and data recovery circuit with a 1/4-rate linear phase detector

A 2.5-Gb/s phase-lock clock and data recovery (CDR) circuit is proposed in system simulation for SONET OC-48 (2.488/2.666-Gb/s) transceiver applications. The CDR circuit exploits 1/4-rate linear phase detector. Making use of this technique the design of voltage controlled oscillator (VCO) facilitate...

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Bibliographic Details
Main Authors: Alavi, S.M., Shoaei, O.
Format: Conference Proceeding
Language:English
Subjects:
1/4 - rate clock
Circuit simulation
Clock and data recovery
Clocks
Detectors
Frequency conversion
linear phase detector
OC-48
Optical transmitters
Phase detection
Power dissipation
SONET
Transceivers
voltage-controlled oscillator (VCO)
Voltage-controlled oscillators
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Description
Summary:A 2.5-Gb/s phase-lock clock and data recovery (CDR) circuit is proposed in system simulation for SONET OC-48 (2.488/2.666-Gb/s) transceiver applications. The CDR circuit exploits 1/4-rate linear phase detector. Making use of this technique the design of voltage controlled oscillator (VCO) facilitates and also it eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recover data.
ISSN:2159-1660
DOI:10.1109/ICM.2005.1590037