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Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table
This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture...
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container_end_page | 58 Vol. 1 |
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container_start_page | 55 |
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creator | Kumaki, T. Kuroda, Y. Koide, T. Jurgen Mattausch, H. Noda, H. Dosaka, K. Arimoto, K. Saito, K. |
description | This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture (Kumaki et al., 2004), which enables fast parallel Huffman encoding. At the same time, the code word table is reconstructed according to the frequency of received input symbols and is up-dated in real-time. Since two the functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. The simulation results for the JPEG application show that the proposed architecture can achieve up to 20% smaller encoded picture sizes, and four times reduced clock cycle numbers for the encoding hardware (8 port case) in comparison to conventional fast Huffman coding architectures. |
doi_str_mv | 10.1109/MWSCAS.2005.1594038 |
format | conference_proceeding |
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The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture (Kumaki et al., 2004), which enables fast parallel Huffman encoding. At the same time, the code word table is reconstructed according to the frequency of received input symbols and is up-dated in real-time. Since two the functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. The simulation results for the JPEG application show that the proposed architecture can achieve up to 20% smaller encoded picture sizes, and four times reduced clock cycle numbers for the encoding hardware (8 port case) in comparison to conventional fast Huffman coding architectures.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2005.1594038</doi></addata></record> |
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subjects | Associative memory CADCAM Clocks Computer aided manufacturing Encoding Frequency Huffman coding Memory architecture Transform coding Very large scale integration |
title | Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table |
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