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Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table

This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture...

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Main Authors: Kumaki, T., Kuroda, Y., Koide, T., Jurgen Mattausch, H., Noda, H., Dosaka, K., Arimoto, K., Saito, K.
Format: Conference Proceeding
Language:English
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creator Kumaki, T.
Kuroda, Y.
Koide, T.
Jurgen Mattausch, H.
Noda, H.
Dosaka, K.
Arimoto, K.
Saito, K.
description This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture (Kumaki et al., 2004), which enables fast parallel Huffman encoding. At the same time, the code word table is reconstructed according to the frequency of received input symbols and is up-dated in real-time. Since two the functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. The simulation results for the JPEG application show that the proposed architecture can achieve up to 20% smaller encoded picture sizes, and four times reduced clock cycle numbers for the encoding hardware (8 port case) in comparison to conventional fast Huffman coding architectures.
doi_str_mv 10.1109/MWSCAS.2005.1594038
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fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1594038</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1594038</ieee_id><sourcerecordid>1594038</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-7b804092b118ffa7f0fe51cd6f8133824008f98f942f6b4f0bd4da48e9c4fdcc3</originalsourceid><addsrcrecordid>eNotkMtqAjEYhUMvUGt9Ajd5gZn-mWRmkqUMbRWULpR2Kbn9NWV0JBOR9umdUuHAt_g4Z3EImTLIGQP1vPpcN7N1XgCUOSuVAC5vyIiVpcy4VOqWTFQtYQhXTNVw9-fE4GpRPZDHvv8GKHjN1IiY1alNITt2MdFmtqJG997Rj-V6QXW0u5C8TafoKXaRzk-Ie32gtnPh8EXPIe1o9LrNUth72h0HhN-hPXhPz110NGnT-idyj7rt_eTKMdm8vmyaebZ8f1s0s2UWFKSsNhIEqMIwJhF1jYC-ZNZVKBnnshAAEtUQUWBlBIJxwmkhvbICnbV8TKb_s8F7vz3GsNfxZ3t9h18AaRBYCQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table</title><source>IEEE Xplore All Conference Series</source><creator>Kumaki, T. ; Kuroda, Y. ; Koide, T. ; Jurgen Mattausch, H. ; Noda, H. ; Dosaka, K. ; Arimoto, K. ; Saito, K.</creator><creatorcontrib>Kumaki, T. ; Kuroda, Y. ; Koide, T. ; Jurgen Mattausch, H. ; Noda, H. ; Dosaka, K. ; Arimoto, K. ; Saito, K.</creatorcontrib><description>This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture (Kumaki et al., 2004), which enables fast parallel Huffman encoding. At the same time, the code word table is reconstructed according to the frequency of received input symbols and is up-dated in real-time. Since two the functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. The simulation results for the JPEG application show that the proposed architecture can achieve up to 20% smaller encoded picture sizes, and four times reduced clock cycle numbers for the encoding hardware (8 port case) in comparison to conventional fast Huffman coding architectures.</description><identifier>ISSN: 1548-3746</identifier><identifier>ISBN: 9780780391970</identifier><identifier>ISBN: 0780391977</identifier><identifier>EISSN: 1558-3899</identifier><identifier>DOI: 10.1109/MWSCAS.2005.1594038</identifier><language>eng</language><publisher>IEEE</publisher><subject>Associative memory ; CADCAM ; Clocks ; Computer aided manufacturing ; Encoding ; Frequency ; Huffman coding ; Memory architecture ; Transform coding ; Very large scale integration</subject><ispartof>48th Midwest Symposium on Circuits and Systems, 2005, 2005, p.55-58 Vol. 1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1594038$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1594038$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kumaki, T.</creatorcontrib><creatorcontrib>Kuroda, Y.</creatorcontrib><creatorcontrib>Koide, T.</creatorcontrib><creatorcontrib>Jurgen Mattausch, H.</creatorcontrib><creatorcontrib>Noda, H.</creatorcontrib><creatorcontrib>Dosaka, K.</creatorcontrib><creatorcontrib>Arimoto, K.</creatorcontrib><creatorcontrib>Saito, K.</creatorcontrib><title>Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table</title><title>48th Midwest Symposium on Circuits and Systems, 2005</title><addtitle>MWSCAS</addtitle><description>This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture (Kumaki et al., 2004), which enables fast parallel Huffman encoding. At the same time, the code word table is reconstructed according to the frequency of received input symbols and is up-dated in real-time. Since two the functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. The simulation results for the JPEG application show that the proposed architecture can achieve up to 20% smaller encoded picture sizes, and four times reduced clock cycle numbers for the encoding hardware (8 port case) in comparison to conventional fast Huffman coding architectures.</description><subject>Associative memory</subject><subject>CADCAM</subject><subject>Clocks</subject><subject>Computer aided manufacturing</subject><subject>Encoding</subject><subject>Frequency</subject><subject>Huffman coding</subject><subject>Memory architecture</subject><subject>Transform coding</subject><subject>Very large scale integration</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>9780780391970</isbn><isbn>0780391977</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkMtqAjEYhUMvUGt9Ajd5gZn-mWRmkqUMbRWULpR2Kbn9NWV0JBOR9umdUuHAt_g4Z3EImTLIGQP1vPpcN7N1XgCUOSuVAC5vyIiVpcy4VOqWTFQtYQhXTNVw9-fE4GpRPZDHvv8GKHjN1IiY1alNITt2MdFmtqJG997Rj-V6QXW0u5C8TafoKXaRzk-Ie32gtnPh8EXPIe1o9LrNUth72h0HhN-hPXhPz110NGnT-idyj7rt_eTKMdm8vmyaebZ8f1s0s2UWFKSsNhIEqMIwJhF1jYC-ZNZVKBnnshAAEtUQUWBlBIJxwmkhvbICnbV8TKb_s8F7vz3GsNfxZ3t9h18AaRBYCQ</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Kumaki, T.</creator><creator>Kuroda, Y.</creator><creator>Koide, T.</creator><creator>Jurgen Mattausch, H.</creator><creator>Noda, H.</creator><creator>Dosaka, K.</creator><creator>Arimoto, K.</creator><creator>Saito, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table</title><author>Kumaki, T. ; Kuroda, Y. ; Koide, T. ; Jurgen Mattausch, H. ; Noda, H. ; Dosaka, K. ; Arimoto, K. ; Saito, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-7b804092b118ffa7f0fe51cd6f8133824008f98f942f6b4f0bd4da48e9c4fdcc3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Associative memory</topic><topic>CADCAM</topic><topic>Clocks</topic><topic>Computer aided manufacturing</topic><topic>Encoding</topic><topic>Frequency</topic><topic>Huffman coding</topic><topic>Memory architecture</topic><topic>Transform coding</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Kumaki, T.</creatorcontrib><creatorcontrib>Kuroda, Y.</creatorcontrib><creatorcontrib>Koide, T.</creatorcontrib><creatorcontrib>Jurgen Mattausch, H.</creatorcontrib><creatorcontrib>Noda, H.</creatorcontrib><creatorcontrib>Dosaka, K.</creatorcontrib><creatorcontrib>Arimoto, K.</creatorcontrib><creatorcontrib>Saito, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Explore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kumaki, T.</au><au>Kuroda, Y.</au><au>Koide, T.</au><au>Jurgen Mattausch, H.</au><au>Noda, H.</au><au>Dosaka, K.</au><au>Arimoto, K.</au><au>Saito, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table</atitle><btitle>48th Midwest Symposium on Circuits and Systems, 2005</btitle><stitle>MWSCAS</stitle><date>2005</date><risdate>2005</risdate><spage>55</spage><epage>58 Vol. 1</epage><pages>55-58 Vol. 1</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>9780780391970</isbn><isbn>0780391977</isbn><abstract>This paper presents a multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table as a novel architecture for high-speed parallel Huffman coding. The multi-port CAM technology exploited is the FMCAM (flexible multi-port content addressable memory) architecture (Kumaki et al., 2004), which enables fast parallel Huffman encoding. At the same time, the code word table is reconstructed according to the frequency of received input symbols and is up-dated in real-time. Since two the functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. The simulation results for the JPEG application show that the proposed architecture can achieve up to 20% smaller encoded picture sizes, and four times reduced clock cycle numbers for the encoding hardware (8 port case) in comparison to conventional fast Huffman coding architectures.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2005.1594038</doi></addata></record>
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subjects Associative memory
CADCAM
Clocks
Computer aided manufacturing
Encoding
Frequency
Huffman coding
Memory architecture
Transform coding
Very large scale integration
title Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T16%3A11%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Multi-port%20CAM%20based%20VLSI%20architecture%20for%20Huffman%20coding%20with%20real-time%20optimized%20code%20word%20table&rft.btitle=48th%20Midwest%20Symposium%20on%20Circuits%20and%20Systems,%202005&rft.au=Kumaki,%20T.&rft.date=2005&rft.spage=55&rft.epage=58%20Vol.%201&rft.pages=55-58%20Vol.%201&rft.issn=1548-3746&rft.eissn=1558-3899&rft.isbn=9780780391970&rft.isbn_list=0780391977&rft_id=info:doi/10.1109/MWSCAS.2005.1594038&rft_dat=%3Cieee_CHZPO%3E1594038%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-7b804092b118ffa7f0fe51cd6f8133824008f98f942f6b4f0bd4da48e9c4fdcc3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1594038&rfr_iscdi=true