An SPU reference model for simulation, random test generation and verification

An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for...

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Bibliographic Details
Main Authors: Watanabe, Y., Sallay, B., Michael, B., Brokenshire, D., Meil, G., Hazim Shafi, Hiraoka, D.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Computer bugs
Decoding
Instruction sets
Microprocessors
Programming
Registers
Robustness
Software testing
Streaming media
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Summary:An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for the random test case generator, for the reference in the verification environment and for the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes at the early stage of the microprocessor development. Also including the reference model in the simulation environment increased the robustness for the random test executions and made it possible to find bugs that are usually difficult to catch.
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2006.1594794