Thread-parallel MPEG-4 and H.264 coders for system-on-chip multi-processor architectures

MPEG-4 and H.264 are rapidly becoming the most popular video coding algorithms for consumer devices. However, this is achieved at the expense of a computationally intensive encoding process and associated power consumption which currently limits their full deployment in portable, cost-sensitive cons...

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Bibliographic Details
Main Authors: Jacobs, T.R., Chouliaras, V.A., Mulvaney, D.J.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Concurrent computing
Encoding
Energy consumption
Frequency
MPEG 4 Standard
Parallel processing
Portable computers
System-on-a-chip
Video coding
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Summary:MPEG-4 and H.264 are rapidly becoming the most popular video coding algorithms for consumer devices. However, this is achieved at the expense of a computationally intensive encoding process and associated power consumption which currently limits their full deployment in portable, cost-sensitive consumer devices. We address the severe performance issue by exploiting thread-level parallelism to share the computational load between multiple processors in a system-on-chip multi-processor configuration. This can lead to significant power savings due to the lower frequency each processor is required to run. For MPEG-4, our custom multi-processor simulator delivers a reduction of 80% to 90% in dynamic instruction count per processor, at 22 processor contexts; for H.264 the theoretical reduction is a near-linear 25 % for four processor contexts, demonstrating a highly balanced multi-threaded implementation
ISSN:2158-3994
2158-4001
DOI:10.1109/ICCE.2006.1598325