Highly scalable flash memory with novel deep trench isolation embedded into highperformance cmos for the 90nm node & beyond

A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for...

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Bibliographic Details
Main Authors: Shum, D., Tilke, A.T., Pescini, L., Stiftinger, M., Kakoschke, R., Han, K.J., Kim, S.R., Hecht, V., Chan, N., Yang, A., Broze, R.
Format: Conference Proceeding
Language:English
Subjects:
CMOS logic circuits
CMOS process
CMOS technology
Etching
Flash memory
Flash memory cells
Isolation technology
Log periodic antennas
Logic arrays
Tunneling
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Summary:A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2005.1609346