Design of high performance PFETs with strained si channel and laser anneal

The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 6...

Full description

Saved in:
Bibliographic Details
Main Authors: Luo, Z., Chong, Y.F., Kim, J., Rovedo, N., Greene, B., Panda, S., Sato, T., Holt, J., Chidambarrao, D., Li, J., Davis, R., Madan, A., Turansky, A., Gluschenkov, O., Lindsay, R., Ajmera, A., Lee, J., Mishra, S., Amos, R., Schepis, D., Ng, H., Rim, K.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Capacitive sensors
CMOS technology
Electronic components
Epitaxial growth
Etching
Optical design
Research and development
Semiconductor device manufacture
Spectroscopy
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D. And for the first time, we have demonstrated that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. Our study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyond
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2005.1609388