Sub-15 ps gate delay with new AC-coupled active pull-down ECL circuit

An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-f/sub T/ ion-implanted silicon bipolar technology. This circuit could be useful as an int...

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Bibliographic Details
Main Authors: Toh, K.-Y., Warnock, J.D., Cressler, J.D., Jenkins, K.A., Danner, D.A., Chen, T.-C.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Delay
Energy consumption
Power dissipation
Power supplies
Radio frequency
Resistors
Ring oscillators
Silicon
Voltage
Online Access:Request full text
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Description
Summary:An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-f/sub T/ ion-implanted silicon bipolar technology. This circuit could be useful as an internal gate operating at low-power and as an I/O gate to drive a large capacitive load at high-power. In both cases, this circuit offers superior power-delay performance compared to conventional ECL circuits.< >
DOI:10.1109/BIPOL.1991.160971