A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

• Published in: IEEE journal of solid-state circuits 2006-04, Vol.41 (4), p.839-850
• Main Authors: Fa Foster Dai, Weining Ni, Shi Yin, Jaeger, R.C.
• Format: Article
• Language: English
• Subjects: CMOS integrated circuits; CMOS technology; data conversion; delta-sigma modulation; digital-to-analog conversion; direct digital synthesizer; Finite wordlength effects; Frequency synthesizers; integrated circuit design; Noise reduction; Noise shaping; Phase measurement; Phase noise; Prototypes; Read only memory; sigma-delta modulation; Size measurement
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.870749

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.