Photoemission identification of emitter resistance for CMOS latch-up hysteresis

The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter re...

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Bibliographic Details
Main Authors: Ming-Jer Chen, Jeng-Kuo Jeng, Ping-Nan Tseng, Nun-Sian Tsai, Ching-Yuan Wu
Format: Conference Proceeding
Language:English
Subjects:
Cathodes
CMOS process
Electric resistance
Hysteresis
Optical microscopy
Photoelectricity
Semiconductor device manufacture
Stimulated emission
Substrates
Testing
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Summary:The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter resistance plays a significant role in producing hysteresis. The authors also describe the three-dimensional effect in terms of pin combinations for the formation of the hysteresis.< >
DOI:10.1109/ICMTS.1990.161748