Loading…

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC

In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this...

Full description

Saved in:
Bibliographic Details
Main Authors: Kerzerho, V., Cauvet, P., Bernard, S., Azais, F., Comte, M., Renovell, M.
Format: Conference Proceeding
Language:English
Subjects:
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 164
container_issue
container_start_page 159
container_title
container_volume
creator Kerzerho, V.
Cauvet, P.
Bernard, S.
Azais, F.
Comte, M.
Renovell, M.
description In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters" (ANC) requires an extremely simple additional circuitry and interconnect
doi_str_mv 10.1109/ETS.2006.1
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1628169</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1628169</ieee_id><sourcerecordid>1628169</sourcerecordid><originalsourceid>FETCH-LOGICAL-i211t-43b1b557fa7355727f46d2265895ee8489efc20ef8fecaf06429dfee8a44951a3</originalsourceid><addsrcrecordid>eNo9jEtPwzAQhC0eEqX0wpXLqvcU24lf3KKkBaSKIiWcK7dZQ6BNSmKevx5XIOYys5pvh5BzRieMUXM5LYsJp1RO2AEZMCF0xJSmh-SUKmkEF1LSo30R04hppU7IqO-faVBspFR8QL7HaWM37eMbwh36j7Z7gdZB1jbv2Hns-vEVpJDPSihx_dTUr4HzbTh6DzZg290GPUKBfv-W5lkPtqkgT0OYbldYVVhB3fyzn1DU99B2UCyyM3Ls7KbH0Z8PycNsWmY30XxxfZul86jmjPkoiVdsJYRyVsXBuHKJrDiXQhuBqBNt0K05Racdrq2jMuGmcqGxSWIEs_GQXPzu1oi43HX11nZfSya5ZtLEPzXrWvA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC</title><source>IEEE Xplore All Conference Series</source><creator>Kerzerho, V. ; Cauvet, P. ; Bernard, S. ; Azais, F. ; Comte, M. ; Renovell, M.</creator><creatorcontrib>Kerzerho, V. ; Cauvet, P. ; Bernard, S. ; Azais, F. ; Comte, M. ; Renovell, M.</creatorcontrib><description>In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters" (ANC) requires an extremely simple additional circuitry and interconnect</description><identifier>ISSN: 1530-1877</identifier><identifier>ISBN: 0769525660</identifier><identifier>ISBN: 9780769525662</identifier><identifier>EISSN: 1558-1780</identifier><identifier>DOI: 10.1109/ETS.2006.1</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit testing ; Costs ; Crosstalk ; Equations ; Instruments ; Intelligent networks ; Semiconductor device measurement ; Space exploration ; System testing ; System-on-a-chip</subject><ispartof>Eleventh IEEE European Test Symposium (ETS'06), 2006, p.159-164</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1628169$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1628169$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kerzerho, V.</creatorcontrib><creatorcontrib>Cauvet, P.</creatorcontrib><creatorcontrib>Bernard, S.</creatorcontrib><creatorcontrib>Azais, F.</creatorcontrib><creatorcontrib>Comte, M.</creatorcontrib><creatorcontrib>Renovell, M.</creatorcontrib><title>"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC</title><title>Eleventh IEEE European Test Symposium (ETS'06)</title><addtitle>ETSYM</addtitle><description>In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters" (ANC) requires an extremely simple additional circuitry and interconnect</description><subject>Circuit testing</subject><subject>Costs</subject><subject>Crosstalk</subject><subject>Equations</subject><subject>Instruments</subject><subject>Intelligent networks</subject><subject>Semiconductor device measurement</subject><subject>Space exploration</subject><subject>System testing</subject><subject>System-on-a-chip</subject><issn>1530-1877</issn><issn>1558-1780</issn><isbn>0769525660</isbn><isbn>9780769525662</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9jEtPwzAQhC0eEqX0wpXLqvcU24lf3KKkBaSKIiWcK7dZQ6BNSmKevx5XIOYys5pvh5BzRieMUXM5LYsJp1RO2AEZMCF0xJSmh-SUKmkEF1LSo30R04hppU7IqO-faVBspFR8QL7HaWM37eMbwh36j7Z7gdZB1jbv2Hns-vEVpJDPSihx_dTUr4HzbTh6DzZg290GPUKBfv-W5lkPtqkgT0OYbldYVVhB3fyzn1DU99B2UCyyM3Ls7KbH0Z8PycNsWmY30XxxfZul86jmjPkoiVdsJYRyVsXBuHKJrDiXQhuBqBNt0K05Racdrq2jMuGmcqGxSWIEs_GQXPzu1oi43HX11nZfSya5ZtLEPzXrWvA</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Kerzerho, V.</creator><creator>Cauvet, P.</creator><creator>Bernard, S.</creator><creator>Azais, F.</creator><creator>Comte, M.</creator><creator>Renovell, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2006</creationdate><title>"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC</title><author>Kerzerho, V. ; Cauvet, P. ; Bernard, S. ; Azais, F. ; Comte, M. ; Renovell, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i211t-43b1b557fa7355727f46d2265895ee8489efc20ef8fecaf06429dfee8a44951a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Circuit testing</topic><topic>Costs</topic><topic>Crosstalk</topic><topic>Equations</topic><topic>Instruments</topic><topic>Intelligent networks</topic><topic>Semiconductor device measurement</topic><topic>Space exploration</topic><topic>System testing</topic><topic>System-on-a-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Kerzerho, V.</creatorcontrib><creatorcontrib>Cauvet, P.</creatorcontrib><creatorcontrib>Bernard, S.</creatorcontrib><creatorcontrib>Azais, F.</creatorcontrib><creatorcontrib>Comte, M.</creatorcontrib><creatorcontrib>Renovell, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kerzerho, V.</au><au>Cauvet, P.</au><au>Bernard, S.</au><au>Azais, F.</au><au>Comte, M.</au><au>Renovell, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC</atitle><btitle>Eleventh IEEE European Test Symposium (ETS'06)</btitle><stitle>ETSYM</stitle><date>2006</date><risdate>2006</risdate><spage>159</spage><epage>164</epage><pages>159-164</pages><issn>1530-1877</issn><eissn>1558-1780</eissn><isbn>0769525660</isbn><isbn>9780769525662</isbn><abstract>In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters" (ANC) requires an extremely simple additional circuitry and interconnect</abstract><pub>IEEE</pub><doi>10.1109/ETS.2006.1</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1530-1877
ispartof Eleventh IEEE European Test Symposium (ETS'06), 2006, p.159-164
issn 1530-1877
1558-1780
language eng
recordid cdi_ieee_primary_1628169
source IEEE Xplore All Conference Series
subjects Circuit testing
Costs
Crosstalk
Equations
Instruments
Intelligent networks
Semiconductor device measurement
Space exploration
System testing
System-on-a-chip
title "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T21%3A42%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=%22Analogue%20Network%20of%20Converters%22:%20A%20DFT%20Technique%20to%20Test%20a%20Complete%20Set%20of%20ADCs%20and%20DACs%20Embedded%20in%20a%20Complex%20SiP%20or%20SOC&rft.btitle=Eleventh%20IEEE%20European%20Test%20Symposium%20(ETS'06)&rft.au=Kerzerho,%20V.&rft.date=2006&rft.spage=159&rft.epage=164&rft.pages=159-164&rft.issn=1530-1877&rft.eissn=1558-1780&rft.isbn=0769525660&rft.isbn_list=9780769525662&rft_id=info:doi/10.1109/ETS.2006.1&rft_dat=%3Cieee_CHZPO%3E1628169%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i211t-43b1b557fa7355727f46d2265895ee8489efc20ef8fecaf06429dfee8a44951a3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1628169&rfr_iscdi=true