Linear-programming-based techniques for synthesis of network-on-chip architectures

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2006-04, Vol.14 (4), p.407-420
• Main Authors: Srinivasan, K., Chatha, K.S., Konjevod, G.
• Format: Article
• Language: English
• Subjects: Applied sciences; Bandwidth; Clocks; Computer architecture; Design automation; Design. Technologies. Operation analysis. Testing; Digital signal processing; Electronics; Energy consumption; Exact sciences and technology; Formulations; Hardware; Input-output equipment; integrated circuit interconnection; Integrated circuit technology; Integrated circuits; Integrated circuits by function (including memories and processors); Linear programming; Links; multiprocessor interconnection; Network synthesis; Network-on-a-chip; Power consumption; Routers; Run time (computers); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Synthesis; System-on-a-chip; Topology; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2006.871762

Application-specific system-on-chip (SoC) design offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC architectures. The optimization objective of the techniques is to minimize the power consumption subject to the performance constraints. We present a two-stage approach for solving the custom NoC synthesis problem. The power consumption of the NoC architecture is determined by both the physical links and routers. The power consumption of a physical link is dependent upon the length of the link, which in turn, is governed by the layout of the SoC. Therefore, in the first stage, we address the floorplanning problem that determines the locations of the various cores and the routers. In the second stage, we utilize the floorplan from the first stage to generate topology of the NoC and the routes for the various traffic traces. We also present a clustering-based heuristic technique for the second stage to reduce the run times of the MILP formulation. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.