CCD image sensor with differential, pyramidal output for lossless image compression

The first integration of a 256*256 buried-channel frame-transfer CCD (charge coupled device) image sensor with CCD-based reformatting circuitry to allow on-chip difference encoding for hierarchical lossless image compression is reported. The 28 frames per second pyramidal pixel output is in 3*3 pixe...

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Bibliographic Details
Main Authors: Kemeny, S., Torby, H., Meadows, H., Bredthauer, R., LaShell, M., Fossum, E.R.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Charge coupled devices
Charge-coupled image sensors
Circuits
Image coding
Image reconstruction
Image storage
Pixel
Power dissipation
Sensor arrays
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Summary:The first integration of a 256*256 buried-channel frame-transfer CCD (charge coupled device) image sensor with CCD-based reformatting circuitry to allow on-chip difference encoding for hierarchical lossless image compression is reported. The 28 frames per second pyramidal pixel output is in 3*3 pixel blocks with the center pixel first. The reformatting circuitry occupies 2% of the active chip area with an estimated power dissipation of 150 mu W at a 30-Hz frame rate.< >
DOI:10.1109/CICC.1991.164120