A background calibration technique for multibit/stage pipelined and time-interleaved ADCs

A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration vol...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2006-06, Vol.53 (6), p.448-452
Main Authors: El-Sankary, K., Sawan, M.
Format: Article
Language:English
Subjects:
Amplification
Analog-digital conversion
Background calibration
Calibration
Capacitors
Converters
Electric potential
Electrical resistance measurement
Error correction
Feedback
Gain
Linearity
Mathematical analysis
multibit/stage analog-to-digital converter (ADC)
Noise cancellation
Operational amplifiers
Performance evaluation
pipelined ADC
time-interleaved ADC (TIADC)
Voltage
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Description
Summary:A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration voltages in a modified conventional multibit multiplying DAC and performing correlation based successive coefficient measurements, a background calibration is performed. This calibration technique does not need an accurate reference voltage or an increasing in the SDAC resolution. A global gain correction essential for time-interleaved ADCs is presented. Simulation results show that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, this technique improves the linearity by several bits in single and multi-channel pipelined ADC
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2006.873831