Investigation of Cu/low-k film delamination in flip chip packages

• Main Authors: Zhai, C.J., Ozkan, U., Dubey, A., Sidharth, Blish, R.C., Master, R.N.
• Format: Conference Proceeding
• Language: English
• Subjects: Acceleration; Delamination; Dielectrics; Failure analysis; Finite element methods; Flip chip; Material properties; Packaging; Performance analysis; Thermal expansion
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2006.1645735

Chip-package-interaction (CPI) induced BEoL (back-end-of-line) delamination has emerged as a major reliability concern with the adoption of Cu/low-k as the mainstream BEoL technology. To study the dependence of Cu/low-k delamination on package underfill material properties and BEoL stack up configuration, a multi-level finite element analysis modeling technique was developed to perform fracture mechanics analysis for a high performance organic flip chip package with Cu/low-k backend technology. Realistic patterned interconnect features were explicitly modeled at the BEoL level. Global analysis revealed the possibility of two failure modes: near-bump delamination and corner delamination. Modeling and experimental results demonstrated that the reduced elastic modulus of the inter-layer dielectric lead to greater probability of CPI-related delamination for both failure modes. Replacing oxide by low-k dielectric resulted in a 3times increase of energy release rate. Hybrid BEoL stack up can effectively reduce the energy release rate by approximately 40% vs. all low-k BEoL stack up. The impact of package underfill modulus on CPI-related reliability is two fold: while reducing underfill modulus helps to prevent corner delamination, it accelerates the near-bump delamination. Higher underfill CTE (coefficient of thermal expansion) increased the risk of Cu/low-k delamination. The modeling also indicated that die size is not the limiting factor for CPI reliability