Performance Trend in Three-Dimensional Integrated Circuits

3DICs are motivated by the expectation of better performance over their 2D counterparts; however, non-idealities threaten to diminish the benefit of multiple tiers. Previous work has predicted the benefit of 3DICs, but have not taken into account the increased temperature and leakage power. This wor...

Full description

Saved in:
Bibliographic Details
Main Authors: Hao Hua, Mineo, C., Schoienfliess, K., Sule, A., Melamed, S., Davis, W.R.
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
Clocks
Integrated circuit interconnections
Performance analysis
Power system interconnection
Power system modeling
Predictive models
Temperature
Thermal resistance
Three-dimensional integrated circuits
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:3DICs are motivated by the expectation of better performance over their 2D counterparts; however, non-idealities threaten to diminish the benefit of multiple tiers. Previous work has predicted the benefit of 3DICs, but have not taken into account the increased temperature and leakage power. This work develops an automated design flow with 2D CAD tools to design 3DICs with the MIT Lincoln Lab 0.18mum three-tier fully depleted silicon on insulator (FDSOI) process (Suntharalingam et al., 2005). This flow uses carefully designed scripts to fill the gap between 2D methodologies and 3D designs. We examine wire-length, timing, clock skew, and total power dissipation, along with temperature, of two benchmark circuits implemented in both 2D and 3D integration. We then extend our observations to the 90nm and 45nm technology nodes with predictive technology model (PTM) and the BSIMSOI model. Experimental results show that the performance of 3DIC, even with the non-idealities, shows up to two-generation advantage over its 2D counterpart with only three tiers
ISSN:2380-632X
2380-6338
DOI:10.1109/IITC.2006.1648642