Next generation radiation-hardened SRAM for space applications

Aeroflex Colorado Springs has developed a monolithic 16M-bit SRAM radiation-hardened to greater than 100 krad(Si) total ionizing dose on TSMC's 0.18mum shallow trench isolation (STI) CMOS line using minimally invasive process intervention. Both single event latchup (SEL) and single event upset...

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Bibliographic Details
Main Authors: Hafer, C., Mabra, J., Slocum, D., Kalkur, T.S.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Circuit synthesis
CMOS process
Error analysis
Error correction
Event detection
Ionizing radiation
Minimally invasive surgery
Random access memory
Single event upset
Springs
Online Access:Request full text
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Summary:Aeroflex Colorado Springs has developed a monolithic 16M-bit SRAM radiation-hardened to greater than 100 krad(Si) total ionizing dose on TSMC's 0.18mum shallow trench isolation (STI) CMOS line using minimally invasive process intervention. Both single event latchup (SEL) and single event upset (SEU) due to charged particle strikes are mitigated by a combination of circuit design techniques, error detection and correction (EDAC), and enhanced layout design rules. The 16M-bit SRAM is SEL immune to greater than 105 MeV-cm 2 /mg. The SEU error rate is less than 2.9times10 -16 errors/bit-day
ISSN:1095-323X
2996-2358
DOI:10.1109/AERO.2006.1655956