Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and...

Full description

Saved in:
Bibliographic Details
Main Authors: Krautz, U., Pflanz, M., Jacobi, C., Tast, H.W., Weber, K., Vierhaus, H.T.
Format: Conference Proceeding
Language:English
Subjects:
Binary decision diagrams
Circuit faults
Circuit simulation
Computer errors
Electrical fault detection
Error correction
Error Detection and Correction
Fault detection
Fault/Error Coverage
Formal Verification
Hardware
Logic
Radiation detectors
Soft Error Injection
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and -correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2006.244062