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A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes
This paper presents a VLSI implementation of a low-density parity check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and (3) the parity equations. This decoder can be programmed in the field, much like an FPGA. We describe the arc...
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| creator | Euncheol Kim Jayakumar, N. Bhagwat, P. Selvarathinam, A. Gwan Choi Khatri, S.P. |
| description | This paper presents a VLSI implementation of a low-density parity check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and (3) the parity equations. This decoder can be programmed in the field, much like an FPGA. We describe the architectural, circuit-level and layout-level details of our implementation. Our design can handle variable rate codes of length up to 1024, and is implemented in a 0.1 mum VLSI fabrication process. Our design has a die size of 12 mm by 8 mm and a power consumption of 7 W. This implementation can be extended to handle longer codes in a partially parallel manner, and allow for on-the-fly modification of the code |
| doi_str_mv | 10.1109/ICASSP.2006.1660818 |
| format | conference_proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1520-6149 |
| ispartof | 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings, 2006, Vol.3, p.III-III |
| issn | 1520-6149 2379-190X |
| language | eng |
| recordid | cdi_ieee_primary_1660818 |
| source | IEEE Xplore All Conference Series |
| subjects | Circuits Decoding Energy consumption Equations Fabrication Field programmable gate arrays Parity check codes Process design Throughput Very large scale integration |
| title | A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes |
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