Low-power high-performance nand match line content addressable memories

Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address comparison. In this paper, the use of dynamic nand match lines is investigated and compared to conventional nor match lines...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2006-08, Vol.14 (8), p.895-905
Main Authors: Chaudhary, V., Clark, L.T.
Format: Article
Language:English
Subjects:
Applied sciences
Associative memory
Buffer storage
Cache memory
Cache tag
CADCAM
Circuit simulation
Computer aided manufacturing
content addressable memory (CAM)
Design. Technologies. Operation analysis. Testing
domino power
Dynamic tests
Dynamics
Electronics
Electronics industry
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
IP (Internet Protocol)
Magnetic and optical mass memories
Mathematical models
nand match line
Pattern matching
Protocols
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Stacks
Storage and reproduction of information
Very large scale integration
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Summary:Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address comparison. In this paper, the use of dynamic nand match lines is investigated and compared to conventional nor match lines in cache applications. To achieve high speed, a hierarchical match line is used. The dynamic stack charge-sharing noise immunity, speed, and actual power savings over a conventional nor match line are investigated using benchmark data. While random patterns are often used when benchmarking CAM match line power, it is shown to be optimistic compared to address trace data, since addresses are highly correlated. It is also shown that proper address input ordering can provide additional power savings. A simple model for the power in dynamic circuit stacks is derived and compared to power simulation data. Additionally, impact on cache tag area and the scaling of the nand stack to future processes is described
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2006.878476