An Integrated Timing and Dynamic Supply Noise Verification Methodology for Nanometer CMOS SoC Designs

A semi-dynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow

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Bibliographic Details
Main Authors: Shimazaki, K., Nagata, M., Sato, K.
Format: Conference Proceeding
Language:English
Subjects:
Circuit noise
Circuit testing
CMOS logic circuits
Delay estimation
Integrated circuit noise
Logic design
Noise measurement
Power supplies
Timing
Voltage
Online Access:Request full text
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Description
Summary:A semi-dynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2006.220788