Algorithms for Detection of Faults in Logic Circuits

Programmed algorithms for test generation and test evaluation are described. The D-notation is introduced and a test generator (DALG) for combinational logic is presented. The sequential case is then examined. "Real life" constraints related to LSI testing are discussed. Two heuristic test...

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Bibliographic Details
Published in:IEEE transactions on computers 1971-11, Vol.C-20 (11), p.1258-1264
Main Authors: Bouricius, W.G., Hsieh, E.P., Putzolu, G.R., Roth, J.P., Schneider, P.R., Tan, C.
Format: Article
Language:English
Subjects:
DALG
fault location
logic circuit diagnosis
logic testing
test generation
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Description
Summary:Programmed algorithms for test generation and test evaluation are described. The D-notation is introduced and a test generator (DALG) for combinational logic is presented. The sequential case is then examined. "Real life" constraints related to LSI testing are discussed. Two heuristic test generators satisfying these constraints are introduced. The iterative test generator (ITG) generates tests by transforming the given sequential circuit into an iterative combinational circuit. The macroblock test generator (MTG) uses the same approach but makes use of complex primitives (latches, triggers, etc.) to represent the circuit to be tested. Both the ITG and the MTG are not always guaranteed to generate good tests for each examined failure, and are used in connection with a test evaluator (simulator). Basic features of this evaluator are discussed.
ISSN:0018-9340
1557-9956
DOI:10.1109/T-C.1971.223125