A Heuristic Algorithm for the Testing of Asynchronous Circuits

This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given.

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Bibliographic Details
Published in:IEEE transactions on computers 1971-01, Vol.C-20 (6), p.639-647
Main Authors: Putzolu, G.R., Roth, J.P.
Format: Article
Language:English
Subjects:
Circuit testing
D-algorithm
diagnosis
LSI
simulation
test generation
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Description
Summary:This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given.
ISSN:0018-9340
1557-9956
DOI:10.1109/T-C.1971.223315