Conditional-Sum Early Completion Adder Logic

A high-speed parallel adder of digitally represented numbers called the conditional-sum early completion adder (CSCA) will be described. The CSCA design is based on the computation of "conditional" sums, carries, and column completion detection logic.

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Bibliographic Details
Published in:IEEE transactions on computers 1980-08, Vol.C-29 (8), p.753-756
Main Authors: Martin, Hufnagel
Format: Article
Language:English
Subjects:
Addition
compute arithmetic
conditional-sum adder
CSA
end-around carry
high speed adder
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Description
Summary:A high-speed parallel adder of digitally represented numbers called the conditional-sum early completion adder (CSCA) will be described. The CSCA design is based on the computation of "conditional" sums, carries, and column completion detection logic.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.1980.1675663