R68-11 Intercommunication of Processors and Memory

Second generation computing systems rarely had an aggregate of peripheral devices with high enough data transfer rates to tax memory speed or to degrade central processor ( CP) performance. Whenever they did, there was no attempt to overlap transfer with computing, and the CP remained idle. But in m...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers 1968-04, Vol.C-17 (4), p.405-406
Main Author: Lauer, H.C.
Format: Article
Language:English
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Second generation computing systems rarely had an aggregate of peripheral devices with high enough data transfer rates to tax memory speed or to degrade central processor ( CP) performance. Whenever they did, there was no attempt to overlap transfer with computing, and the CP remained idle. But in many third generation systems, there are several processors-both I/O devices and arithmetic units-operating asynchronously and independently, each of which has a high transfer rate to main memory. Thus, the question of designing sufficient bandwidth into memories and buses is significant. Experience with some of the commercial multiprocessing systems (e. g., UNIVAC 1108 or IBM 360/67) shows, however, that sufficient bandwidth is not enough. The system must be organized so that the full bandwidth, or at least a large fraction of it, can be used effectively. It is this problem to which the author has ably addressed his paper.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.1968.226894