Low power architectures using localised non-volatile memory and selective power shut-down

A method and associated circuit and architectural implementations to reduce the power dissipation for the digital part of a system-on-a-chip (SOC) while maintaining the overall system performances (such as speed) unaffected are described. An alternative application is to provide fast recovery from a...

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Bibliographic Details
Main Authors: Secareanu, R.M., Hartin, O.
Format: Conference Proceeding
Language:English
Subjects:
Circuits and systems
Clocks
Digital systems
Magnetic circuits
Magnetic materials
Nonvolatile memory
Power dissipation
Power generation
Semiconductor materials
System-on-a-chip
Online Access:Request full text
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Description
Summary:A method and associated circuit and architectural implementations to reduce the power dissipation for the digital part of a system-on-a-chip (SOC) while maintaining the overall system performances (such as speed) unaffected are described. An alternative application is to provide fast recovery from a power shut-down event up to the level of instruction (or clock cycle) execution
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2006.1692601